Study of FPGA for Hosting Interface and Control Logic

A task to miniaturize controller for Electro Mechanical Actuator (EMA) using FPGA was considered by Research Centre Imarat (RCI). The CORI of erstwhile PES Institute of Technology (PESIT), the present PES University, was entrusted to carry out a Study of FPGA for Hosting Interface and Control Logic for Controlling EMA using Brushless DC (BLDC) Motor. We bring out in this write up the hardware and software developed for this study project, the project execution methodology and the completion of project. Block diagram shown in following figure represents the total system where a BLDC has to drive an EMA and the digital section is to be realized using FPGA.

Proposed System by CORI, PESIT for RCI

CORI developed Hardware

In the total study project, CORI developed the following circuit hardware:

4-channel ADC board

4-channel DAC board

16-channel ADC, DAC, Hall sensor interface and BLDC driver interface

BLDC motor driver for a 15-W BLDC motor

Illustrate the PCB fabricated and tested

CORI developed Software for FPGA

CORI developed the following software for FPGA:

ADC data acquisition for 16-channels at 30-Ksamples / second simultaneously.
Limit checking for each channel to take care of safety of BLDC and EMA
Carry out averaging of the data for 1-ms control loop
Implement controller for current loop
Collect Hall sensor data and carry out BLDC top and bottom switch control
Make use of Current loop output and carry out PWM control for BLDC
Hall sensor fault state identification and take corrective action for BLDC drive signals

Realization Steps

In order to ensure successful realization of hardware and software, we followed the steps listed below:

Design PCB for 4-channel ADC with bridge between digital and analog ground. Ensure that we are able to go to the 14-bit measurement capability
Do similar trials with 4-channel DAC
Carry out loop test with ADC and DAC and see that the scale factor remains constant
Based on the above trials design 16-channel ADC and DAC board and test
Carry out current loop design with simulated motor armature resistance and inductance for BLDC motor. Carry out current loop hardware test and ensure that it matches with design value
Carry out PWM based speed control of BLDC using designed motor driver using Hall sensor signals
Hall sensor fault state identification and take corrective action for BLDC drive signals
Carry out simulation using SIMULINK for EMA movement profiles

The project was completed with development of ADC, DAC, Hall sensor signal handling and BLDC driver interface.

Necessary software was developed for controlling ADC data acquisition, DAC data output, Hall sensor data handling and BLDC drive signal generation. One M-Tech student and 3-B.E students were involved in the project. One Research Assistant was also involved apart from the Professors. It was a fruitful project that helped CORI to gain valuable insight into BLDC based control using fully software based control loops.

Study of FPGA for Hosting Interface and Control Logic

Study of FPGA for Hosting Interface and Control Logic

CORI developed Hardware

CORI developed Software for FPGA

Realization Steps

In order to ensure successful realization of hardware and software, we followed the steps listed below:

The project was completed with development of ADC, DAC, Hall sensor signal handling and BLDC driver interface.

PESU Bot